IBM Technical Disclosure Bulletin, Vol. 17, #1, June 1974, pp. 245-247, describes a memory system fabrication scheme using a laser to form connections in which the connections are formed through an overlying oxide layer without removal of a portion of the oxide layer so that metal lines on the surface of the oxide are connected to underlying, diffused signal tracks.
U.S. Pat. No. 3,801,910 issued Apr. 2, 1974 to H. F. Quinn and assigned to the same assignee as is the present invention, discloses a method of using a photodiode to temporarily interconnect a selected circuit to a test point. Specifically, this patent teaches that by shining a light on a photodiode it can be made to conduct and temporarily cause a circuit to be connected to a test bus.
U.S. Pat. No. 4,140,967 issued Feb. 20, 1979 to B. S. Balasubramanian et al and assigned to the same assignee as the present invention, discloses a programmable logic array and a method of testing it after it is programmed.
U.S. Pat. No. 4,233,671 issued Nov. 11, 1980 to L. Gerzberg et al, discloses read-only memory and integrated circuits and a method of programming them by laser means.
U.S. Pat. No. 3,956,698 issued May 11, 1976 to P. R. Malmberg et al and its continuation-in-part U.S. Pat. No. 4,053,833 issued Oct. 11, 1977, discloses a method for testing an integrated circuit by switching on a diode. Thus, these patents are similar to the teaching of U.S. Pat. No. 3,801,910. Subsequently, Malmberg short circuits the diode by a selected metallization step with standard vapor or sputter deposition techniques.
IBM Technical Disclosure Bulletin, Vol. 18, #4, September 1975, pp. 1047-1048, teach a program power proportioning scheme for programmable logic arrays.
In programmable logic arrays circuits such as latches or decoder circuits are partially or totally inoperable prior to the programming of the array and thus normally untestable until after the array has been programmed.
The present invention overcomes this problem and permits the testing of such circuits prior to the programming of the associated logic array.